News

Apr 22, 2023

MIPS taps Siemens FPGA for RISC

Under the collaboration, MIPS is using the Siemens Veloce proFPGA platform to

Under the collaboration, MIPS is using the Siemens Veloce proFPGA platform to demonstrate MIPS cores, including the eVocore P8700. The core, the first Out-of-Order (OoO) processor with coherent multi-threaded, multi-core and multi-cluster scalability, has already been adopted for applications including autonomous driving and advanced driver assistance systems (ADAS).

Running the RISC-V CPUs on the proFPGA platform enables developers to validate their end systems before silicon. Customers can add their custom logic and accelerators and validate their system-on chip (SoC) for optimal functionality. In addition, Siemens’ Veloce proFPGA platform will give customer software teams full access to the platform's prototyping hardware system, software tools, and debug trace hooks, enabling early software development and hardware-software codesign.

"As a growing number of SoC designers are moving to RISC-V for their future designs, we are seeing increasing interest in our eVocore processors because of the unrivaled level of scalability they provide," said Desi Banatao, CEO of MIPS. "We are delighted to collaborate with Siemens to enable our customers to benefit from all the features and tools of our best-in-class eVocore P8700 together with the scalable capacity and flexibility offered by Siemens’ Veloce proFPGA platform."

Developers can also add their own accelerators to systems with the P8700 while maintaining coherency alongside up to 64 clusters and 8 cores per cluster and 2 threads per core.

The desktop FPGA prototype can be used with various types of workloads, with onboard testbenches and in-circuit connections to external hardware as Ethernet generators or PCI Express buses. This enables MIPS to support multiple configurations, starting with a single core, single threaded CPU up to multi-core, multi-cluster configurations.

"The increasing complexity of SoC designs requires more substantial prototyping tools," said Jean-Marie Brunet, vice president and general manager of HW-assisted verification at Siemens Digital Industries Software. "We are pleased to help MIPS customers and developers keep up with the accelerating pace of innovation by providing powerful and scalable prototyping solutions tailored to their use cases, from IP to sub-system to SoC."

www.mips.com; www.siemens.com